Efficient Reconfigurable Modular Multipliers for Post-Quantum Digital Signatures

Post-quantum cryptography (PQC) based digital signature schemes are gaining popularity after the National Institute of Standards and Technology (NIST) identified some quantum-resistant schemes. These schemes heavily rely on a multiplication operation in a finite field over different modulus <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(q)$</tex> sizes and values. Moreover, parameter sets for these schemes are updated with each NIST submission round, thus a configurable modular multiplier is in high demand and capable of computing different PQC-based digital signature schemes. This work presents novel modular multipliers by introducing modifications in the interleaved multiplication algorithm. The introduced modifications mainly reduce critical path delay and resource consumption by preserving the generality of the design. We present two efficient designs for common PQC algorithms <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$q$</tex> sizes (5–32 bits). These are implemented on the Xilinx Virtex-7 FPGA platform and demonstrate significant improvement in area-latency product and efficiency than state-of-the-art. An up to 30.6% reduction in area is achieved once these are integrated into matrix-vector architecture.