Peripheral Block Extension of a Reconfigurable 8T SRAM In-Memory Computing Macro for High-Throughput MAC Operations

In-Memory Computing (IMC) is a solution to data-transfer bottlenecks by allowing computations within the memory itself. 8T SRAM bitcells are used in a digital IMC architecture for improved read stability and immunity to noise and process variations. Among the state-of-the-art digital 8T SRAM IMC works is the Bit-Parallel Searching and Computing In-Memory (BP-SCIM) macro that supports the most number of operations - content-addressable memory (CAM) search, Boolean logic, and arithmetic. Its bit-parallel approach allows for linear-time multiplication and division, and separate compute and write cycles give a higher clock frequency than other works. However, it only supports multiply-accumulate (MAC) operations by separate multiplication and addition operations, reducing its efficiency. Hence, in this work, the macro was reimplemented under the GlobalFoundries (GF) 22 nm FDSOI CMOS technology, achieving a lower latency, higher throughput, and a maximum operating frequency of 900 MHz in arithmetic operations. The macro was also extended with a peripheral block that improved the performance in MAC operations, decreasing the latency and increasing the throughput by 156 % with an average energy efficiency of 4.86 GOPS/W.