Matching Improvements in Capacitor Arrays for Precision Charge Redistribution SAR ADCs

This paper presents a series of techniques for improving the intrinsic matching of large capacitor arrays used in charge redistribution C-DACs for successive approximation register (SAR) analog to digital converters (ADCs). The analysis takes an in-depth look at the geometry of the capacitors implemented in a 40nm CMOS process, minimising sources of mismatch, analysing in detail the impact of finger spacing, metal width, and finger length. The impact of local array gradient is also considered in both the X and Y dimension, providing a recommendation for preventing parabolic gradient effects. The random and systematic mismatch errors are quantified and decorrelated, with the systematic element showing strong geometry dependency, being the dominant source of error in specific configurations. The approach overcomes the gain errors introduced by the usage of a sub-DAC (typically 1-5% error). The capacitors are implemented in a commercial 40nm process and bonded in a QFN package. The measurement results show 4 to 7 times improvement in the total mismatch error with respect to conventional MOM capacitor arrays. The equivalent SNR improvement within an uncalibrated SAR ADC is 16.7dB, which is sufficient for achieving 16-bit uncalibrated linearity