All-MOSFETs Current Reference Featuring High-Order Segmented Curvature Compensation

Achieving enhanced robustness of Current References (CRs) against Process-Voltage-Temperature (PVT) variations still represents a demanding task for integrated circuit designers. Specifically, while Beta-Multiplier (BM) implementations may ensure small process spread, temperature dependency is particularly challenging to minimize. In this respect, we hereby present a solution based on modified BM-CR cores featuring a high-order segmented curvature correction scheme. Electrical simulations of a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.18-\mu \mathrm{m}$</tex> CMOS design with 469-nA output current show a Temperature Coefficient (TC) of 76.1 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{ppm}/^{\circ} \mathrm{C}$</tex> (average value across Monte Carlo runs), reaching a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\times 4.5$</tex> reduction with respect to the same BM-CR without curvature compensation. The relative standard deviation of the output current and the line sensitivity are equal to 0.80% and 3.27%/V, respectively. These results suggest the proposed approach as a useful option for PVT-robust CR implementations.