Digital Architecture for the n-mode Tensor-Matrix Multiplication Based on Pipelined Computing Units

Compact digital circuitry supporting data processing is a key requirement of modern engineering. This pa-per addresses the design of digital architectures for a crucial operation in multi-linear algebra: the n-mode tensor-matrix product, implemented in fixed-point representation. A pipelined architecture that optimizes throughput and balances area and energy consumption is proposed. A cost-effective classifier based on this architecture was deployed on an embedded system. Ex-perimental tests conducted on a Kintex-7 FPGA demonstrate that the circuit achieves efficient digital implementations, providing real-time performance on benchmark applications with power consumption lower than 130 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$mW$</tex>. This implementation proves to be more efficient than its non-pipelined counterpart.