A 0.9V CMOS Voltage Reference with 0.41% Untrimmed Accuracy and 44.7 ppm/°C TC from -35°C to 130°C

A stable bandgap voltage reference (BGR) with low power consumption and small area is essential for the long-term operation and miniaturization of Internet-of-Things sensors and implantable devices. Recently, CMOS-only circuits [1] –[4] have been proposed to meet this requirement. However, when using the threshold voltage $\left(\mathrm{V}_{\mathrm{TH}}\right)$ of MOSFETs as a complementary-to-absolute-temperature (CTAT) voltage ($\mathrm{V}_{\text {CTAT}}$) in a reference, the inherent variability of $\mathrm{V}_{\text {TH}}$ would introduce process dependency. To compensate the process variation in $\mathrm{V}_{\text {TH,}}$, a hybrid architecture combining BGR and CMOS reference with dimension-induced side effects [5] has been proposed. Nevertheless, the compensation relies on a BJT-generated proportional to faster-skewed process (PTFP) voltage (VPTFP), constraining the minimum supply voltage to 1 V. Alternatively, [1] utilizes the threshold difference between transistors in stacked diode MOS transistors (SDMT) to generate an output that is robust to PVT variations without using BJTs, effectively reducing the supply voltage to 0.9 V. Nonetheless, since Vctat and Vptap are generated within the same SDMT, individual optimization of TC curvature without affecting process compensation is complicated, resulting in a high temperature coefficient (above $60 \mathrm{ppm} /{}^{\circ} \mathrm{C}$) from -40 to $130^{\circ} \mathrm{C}$. This paper presents a compensation method that eliminates the use of BJT by separating PTAT and CTAT generators from a single branch. The proposed technique introduces VPTFP to the output through the $\vee_{\text {TH}}$ difference of the input transistor pair within the PTAT-embedded amplifier, while enhancing Vctat linearity with a nonlinear CTAT current. Fabricated in 180nm CMOS, the untrimmed voltage reference exhibits a 0.4% standard deviation and a TC of $44.7 \mathrm{ppm} /{}^{\circ} \mathrm{C}$ from $-35^{\circ} \mathrm{C}$ to $130^{\circ} \mathrm{C}$, with a mean output of 524 mV.

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Publication Details

Published
2024-11-18
DOI
https://doi.org/10.1109/a-sscc60305.2024.10848578
Citations
2
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.37
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article

A 0.9V CMOS Voltage Reference with 0.41% Untrimmed Accuracy and 44.7 ppm/°C TC from -35°C to 130°C

Xuanlin Chen, Jiangchao Wu, Man Kay Law, Bo Wang
2 citations
Analog and Mixed-Signal Circuit Design
0.37
article

A 0.9V CMOS Voltage Reference with 0.41% Untrimmed Accuracy and 44.7 ppm/°C TC from -35°C to 130°C

Xuanlin Chen, Jiangchao Wu, Man Kay Law, Bo Wang
article en
2 citations

Abstract

A stable bandgap voltage reference (BGR) with low power consumption and small area is essential for the long-term operation and miniaturization of Internet-of-Things sensors and implantable devices. Recently, CMOS-only circuits [1] –[4] have been proposed to meet this requirement. However, when using the threshold voltage $\left(\mathrm{V}_{\mathrm{TH}}\right)$ of MOSFETs as a complementary-to-absolute-temperature (CTAT) voltage ($\mathrm{V}_{\text {CTAT}}$) in a reference, the inherent variability of $\mathrm{V}_{\text {TH}}$ would introduce process dependency. To compensate the process variation in $\mathrm{V}_{\text {TH,}}$, a hybrid architecture combining BGR and CMOS reference with dimension-induced side effects [5] has been proposed. Nevertheless, the compensation relies on a BJT-generated proportional to faster-skewed process (PTFP) voltage (VPTFP), constraining the minimum supply voltage to 1 V. Alternatively, [1] utilizes the threshold difference between transistors in stacked diode MOS transistors (SDMT) to generate an output that is robust to PVT variations without using BJTs, effectively reducing the supply voltage to 0.9 V. Nonetheless, since Vctat and Vptap are generated within the same SDMT, individual optimization of TC curvature without affecting process compensation is complicated, resulting in a high temperature coefficient (above $60 \mathrm{ppm} /{}^{\circ} \mathrm{C}$) from -40 to $130^{\circ} \mathrm{C}$. This paper presents a compensation method that eliminates the use of BJT by separating PTAT and CTAT generators from a single branch. The proposed technique introduces VPTFP to the output through the $\vee_{\text {TH}}$ difference of the input transistor pair within the PTAT-embedded amplifier, while enhancing Vctat linearity with a nonlinear CTAT current. Fabricated in 180nm CMOS, the untrimmed voltage reference exhibits a 0.4% standard deviation and a TC of $44.7 \mathrm{ppm} /{}^{\circ} \mathrm{C}$ from $-35^{\circ} \mathrm{C}$ to $130^{\circ} \mathrm{C}$, with a mean output of 524 mV.

University of Macau (MO), Hamad bin Khalifa University (QA)
Affordable and clean energy
Openalex Percentile: Top 41%
Analog and Mixed-Signal Circuit Design
0.37
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