A 39-Gb/s PAM-3 Transmitter and ADC-Based Receiver Chipset in CMOS Technologies

Recently, the pulse amplitude modulation (PAM) signaling has been extensively applied in wireline communication. Comparing with the PAM-4 counterpart, the PAM-3 signaling provides another solution to increase the data rate with less SNR degradation and linearity requirement. It is adopted in the recent USB4 2.0 specification with $40-\mathrm{Gb} / \mathrm{s}$ per-lane data rate [1]. This paper presents a $39-\mathrm{Gb} / \mathrm{s}$ PAM3 TXIRX chipset in 40 - and $28-\mathrm{nm}$ CMOS technologies. The TX and RX achieves 2.2- and 4.3-pJ/b energy efficiency, respectively. The RX adopts the ADC-DSP architecture with digital equalization to achieve 1E-8 pre-FEC BER under $27-\mathrm{dB}$ loss channel.