An All-digital, 3.68 mV/LSB Voltage Sensor based Droop Prediction and Fast Mitigation System in 28nm CMOS

In digital SoCs, voltage droop caused by work-load variations can reduce the voltage by over 100 mV in about 10 ns [1]. However, to capture the details during the droop as shown in Fig. 1 top, previous voltage sensors still face challenges: 1) Their resolution is limited by the sensitivity of the standard cells in Voltage-to-Time Converter (VTC); 2) Low sampling rate and VTC is affected by PVT (Process, Voltage-nonlinear, Temperature) variations [2–5]. On the other hand, traditional LDOs struggle to effectively mitigate droop due to the loop-latency and the fine regulation strategy [6–10]. Current injection techniques have been proposed to address the droop issue, but they are still limited by the detection and control latency, and it is challenging to determine the precise amount of current to inject.