FPGA-based Implementation of Deep Reinforcement Learning for Heat Recovery Chiller Optimization

This paper presents the FPGA implementation of a Deep Reinforcement Learning (DRL) algorithm to optimize Heat Recovery Chiller (HRC) systems. The proposed hardware DRL implementation, based on the Actor-Critic algorithm, enhances the performance and efficiency of HRC systems within a DRL framework. The implementation results on the Xilinx UltraScale+ ZCU104 board demonstrate high performance compared to similar previous works, operating at 266 MHz with a dynamic power consumption of 1.697 W.