PRIM-CAEFA: A 64K-spin Packet-based Reconfigurable Ising Machine with Cross-problem Adjustment-free Energy Feedback Annealing

Ising machine is designed to solve optimization problems. State-of-the-art CMOS Ising machines [1] –[7] are divided into two types: all-to-all interaction and sparse interaction (Fig. 1 top). The former type is more desirable for solving a variety of problems with complex interaction patterns, but it suffers from performance and hardware resources scalability issue [2], [5]. In contrast, the sparse degree (number of interactions) of the latter type leads to better performance and scalability [1], [3] –[5], [7], however, without minor embedding (extra mapping effort, degraded accuracy, replica spins), the limited degree results in limited applicable problem sets. e-Chimera [1] and Flexible spin processing elements [3] enlarge the flexibility of sparse interaction Ising machines, yet the problems that can be solved by machine with limited number of graph topologies [1] or fixed degree global interactions [3] are still less than the all-to-all interaction machine; all-to-all interaction is more desirable for a variety of optimization problems. Latch-based circuits are suitable for implementing all-to-all interaction. However, due to the deterministic property of latch, external annealing algorithms, which require tedious adjustment of the hyperparameters for each problem, should be implemented. To leverage the advantages of two types Ising machine and avoid the time-consuming hyperparameter adjustment, we propose a Packet-based Reconfigurable Ising Machine (a spin includes the spin itself and packets, where the packet includes the characteristics of spin) with Cross-problem Adjustment-free Energy Feedback Annealing (PRIM-CAEFA) (Fig. 1 bottom), featuring 1) reconfigurable and scalable a) spin number (up to 64 K within one chip) and b) interaction number (all-to-all interaction for versatile applications, sparse random interaction for adaptable computation and performance); the global sparse random degree is suitable for solving all kinds of problem without extra mapping effort, redundant computation or area consuming. 2) only 10 iterations to reach 90% of the minimum energy. 3) general usage annealing without tedious adjustment of the hyperparameters. 4) the capability of solving integer factorization on CMOS Ising machine.

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Published
2024-11-18
DOI
https://doi.org/10.1109/a-sscc60305.2024.10849084
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
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article

PRIM-CAEFA: A 64K-spin Packet-based Reconfigurable Ising Machine with Cross-problem Adjustment-free Energy Feedback Annealing

Jerald Yoo, Longyang Lin, Chne-Wuen Tsai, Jiaer Chen et al.
Advanced Memory and Neural Computing
article

PRIM-CAEFA: A 64K-spin Packet-based Reconfigurable Ising Machine with Cross-problem Adjustment-free Energy Feedback Annealing

Jerald Yoo, Longyang Lin, Chne-Wuen Tsai, Jiaer Chen, Zhongqi Li, Jiamin Li, Yingna Huang
article en

Abstract

Ising machine is designed to solve optimization problems. State-of-the-art CMOS Ising machines [1] –[7] are divided into two types: all-to-all interaction and sparse interaction (Fig. 1 top). The former type is more desirable for solving a variety of problems with complex interaction patterns, but it suffers from performance and hardware resources scalability issue [2], [5]. In contrast, the sparse degree (number of interactions) of the latter type leads to better performance and scalability [1], [3] –[5], [7], however, without minor embedding (extra mapping effort, degraded accuracy, replica spins), the limited degree results in limited applicable problem sets. e-Chimera [1] and Flexible spin processing elements [3] enlarge the flexibility of sparse interaction Ising machines, yet the problems that can be solved by machine with limited number of graph topologies [1] or fixed degree global interactions [3] are still less than the all-to-all interaction machine; all-to-all interaction is more desirable for a variety of optimization problems. Latch-based circuits are suitable for implementing all-to-all interaction. However, due to the deterministic property of latch, external annealing algorithms, which require tedious adjustment of the hyperparameters for each problem, should be implemented. To leverage the advantages of two types Ising machine and avoid the time-consuming hyperparameter adjustment, we propose a Packet-based Reconfigurable Ising Machine (a spin includes the spin itself and packets, where the packet includes the characteristics of spin) with Cross-problem Adjustment-free Energy Feedback Annealing (PRIM-CAEFA) (Fig. 1 bottom), featuring 1) reconfigurable and scalable a) spin number (up to 64 K within one chip) and b) interaction number (all-to-all interaction for versatile applications, sparse random interaction for adaptable computation and performance); the global sparse random degree is suitable for solving all kinds of problem without extra mapping effort, redundant computation or area consuming. 2) only 10 iterations to reach 90% of the minimum energy. 3) general usage annealing without tedious adjustment of the hyperparameters. 4) the capability of solving integer factorization on CMOS Ising machine.

Seoul National University (KR), National University of Singapore (SG), Southern University of Science and Technology (CN)
National Research Foundation
Affordable and clean energy
Openalex Percentile: Top 76%
Advanced Memory and Neural Computing
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