A 860mV and 73.5Ppm/°C Voltage Reference that Relies on Back-Gate Biasing Techniques in 28nm FD-SOI Technology
This paper discusses the development of a new topology voltage reference in Fully Depleted Silicon-On-Insulator (FD-SOI) technology. The voltage reference described in this paper is based on threshold voltage subtraction techniques, PTAT and CTAT voltage addition and transistor's back-gate biasing in 28nm FD-SOI technology. It has a 860mV output and achieves a performance of 73.5ppm/°C (T=-50°C to 150°C) under a supply voltage of 1V.
Authors
- Yann Deval (ORCID: https://orcid.org/0000-0002-7358-8904)
- François Rivet (ORCID: https://orcid.org/0000-0002-6003-4208)
- Hervé Lapuyade
- Maxime Guillot
Institutions
- Centre National de la Recherche Scientifique (FR)
- Université de Bordeaux (FR)
- Laboratoire de l'Intégration du Matériau au Système (FR)
- Institut Polytechnique de Bordeaux (FR)
Publication Details
- Published
- 2024-11-18
- DOI
- https://doi.org/10.1109/icecs61496.2024.10849174
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00