A 45-fs_rms Accumulated Jitter PLL Using Advanced Design Techniques for PCIe Gen6 Reference Clock Generation in 2 nm MBCFET Technology

The continuous advancement of technology has led to the increase in data rates of high-speed serial links like PCIe, MPHY, USB and Ethernet, with stringent random jitter (RJ) specifications. The PCIe protocol, for instance, necessitates a reference clock frequency of 100 MHz for its Tx/Rx PLLs and CDR. To achieve this, a temperature-compensated crystal oscillator (TXCO) with low jitter can be used, but it incurs additional overhead on power (to drive the TXCO) and area (increase in number of soldier balls for flip-chip integration), thereby escalating production costs [1]. An alternative is to use an on-chip dedicated low-jitter PLL with tens of MHz of TXCO (low-cost). The system-on-chip (SoC) needs a fast lock time for this PLL, so it should support fast bring-up to meet PCIe compliance requirements. The SoC environment is also known for its severe temperature drift, which can reach up to $60^{\circ} \mathrm{C}$ and more. In automotive applications, the PLL requires even wider range of temperature drift, compared to mobile applications. In addition, the absence of thick-oxide devices in 2 nm middle bridge-channel FET (MBCFET) technology poses a design challenge for high-performance analog blocks powered by 1.2 V supply. To overcome these challenges, we propose a low-jitter PLL for PCIe reference clock generation that includes optimization techniques for low jitter and low area. A reliability-aware analog design approach for 1.2 V tolerant designs and a fast-locking scheme based on fully-synthesizable, digital bang-bang automatic frequency calibration (AFC) are presented. Also, advanced layout techniques are suggested to achieve the tracking capability of the on-chip temperature drift. The proposed PLL is fabricated in 2 nm MBCFET technology with an active area of $0.048 \mathrm{~mm}^{2}$, and it achieves a 45-$\mathrm{fS}_{\mathrm{r} m \mathrm{~m}}$ accumulated jitter for the PCIe-Gen6 application, a dynamic temperature range (DTR) of $-45^{\circ} \mathrm{C}$ to $125^{\circ} \mathrm{C}$ and a lock time of $6 \mu \mathrm{~s}$.