A 0.0006-mm² 0.13-pJ/bit 9–21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1:3 DEMUX in 65-nm CMOS

The growing demand for data throughput has led to the rapid development of serial I/O interfaces such as PCle, USB, and JESD204. As a key component, a compact and energy-efficient high-speed clock and data recovery (CDR) circuit is necessary. Figure 1 (top) shows the block diagram of the conventional CDR with a DFF-based phase detector (PD) and its severe flaws in tradeoffs among jitter, area, and retiming. To surmount these challenges, [1] proposes an inductor-less CDR utilizing a primary-secondary (P-S) sampler as the PD (Fig. 1, middle). In this way, the low-pass filter (LPF) is eliminated and a wide loop bandwidth is achieved, breaking the tradeoff between jitter generation and jitter tolerance (JTOL). However, due to the full-rate operation, high-speed rail-to-rail clocks are required. At extreme data rates, the power consumption for clock generation and distribution would increase sharply. Additionally, the inherent multi-phase clocks from the ring oscillator (RO) are used for retiming skew compensation, but the accuracy is pretty limited.