A Single-Ended SAR ADC with Low-Energy Differential Switching for X-Ray Imagers

This work presents a SAR ADC architecture designed for single-ended-to-differential conversion with low-energy switching and area efficiency. By incorporating top and bottom sampling techniques, the architecture achieves seamless conversion without the need for extra DAC hardware. It offers configurable fully-differential or single-ended modes by means of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\mathrm{c}\mathrm{m}}$</tex> -based switching. With 75 % reduced total capacitance compared to conventional method, consistent energy savings are achieved across configurations. Implemented in 130 nm CMOS, this design features an array of 48 ADCs and custom on-chip voltage references integrated within the SparkPix-S ASIC, a device tailored for X-ray imagers. With a nominal sampling rate of 5 MSPS and 1.2 V supply voltage, the achieved SNDR is 54.5 dB, with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$+0.98/-0.86$</tex> LSB of DNL and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$+0.83/-1.26$</tex> LSB of INL. The core SAR ADC average power consumption is 96 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathrm{W}$</tex>, resulting in a FOM of 40.1 fJ/conv-step, all within a compact active area of 0.0212 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.