A Bit Serial Accelerator Architecture for Efficient ML Compute in Area, Power and Cost Constrained Sensors

This paper describes a bit-serial MAC accelerator building block architecture that is optimized for low power and cost constrained systems. The architecture is implemented with both a mixed signal and fully digital approach to compare performance. The accelerators are implemented in 40 nm CMOS and achieve up to 12.5 TOPS/W at 0.65 V supply voltage and 15 MHz clock frequency.