A 4-Phase Integrated Voltage Regulator with In-Package Inductors Achieving 89.0% Peak Efficiency and 65% Droop Improvement for 6A/2ns Transient
With the advancement of artificial intelligence (AI), computing processors and GPUs have dramatically increased their current consumption. Significant power ($I^{2} R$) losses and heat can be generated on the routing path between the voltage regulators (VRs) and the processors, as shown in Fig. 1. To address this issue, VRs are required to possess high current density and high efficiency, ensuring they can be placed closest to the processors and do not generate excessive heat. The inductors in VRs present the greatest challenge in minimizing the size due to their low power density and difficulty of integration. Fully integrated voltage regulators (FIVRs) in [1], [2] employed high-performance in-package air-core/magnetic inductors to achieve high current density and efficiency. However, they require expensive and exclusive inductor fabrication processes. In [3], a switched-capacitor voltage regulator (SCVR) was adopted to avoid inductors and establish a compact volume. However, deeptrenched capacitors were required and slow transient responses were observed. Additionally, multiphase FIVRs utilizing bond-wires as inductors [4], [5] have been explored, but their maximum output current (lout) is limited, and bond-wires are incompatible with flip-chip packages. Moreover, VRs must have fast transient response to stabilize output voltage during extreme load fluctuations in processors while current transient-enhancement techniques cannot cope with various transient conditions and may still experience large undershoot.
Authors
- Ka Nang Leung (ORCID: https://orcid.org/0000-0002-9921-3211)
- Chenzhou Ding (ORCID: https://orcid.org/0009-0008-6889-8984)
- Shan Jiang (ORCID: https://orcid.org/0000-0002-6942-9484)
- Junyi Ruan (ORCID: https://orcid.org/0009-0000-1582-8255)
- Faen Liu
- Kai Yuan (ORCID: https://orcid.org/0000-0002-4507-1510)
- Junmin Jiang (ORCID: https://orcid.org/0000-0001-6529-0422)
- Tao Liu (ORCID: https://orcid.org/0000-0003-1385-733X)
- Xun Liu (ORCID: https://orcid.org/0000-0002-6115-8886)
- Tiantian Tang (ORCID: https://orcid.org/0009-0004-8033-8286)
- Yelei Xie
Institutions
- Chinese University of Hong Kong (HK)
- Southern University of Science and Technology (CN)
- Chinese University of Hong Kong, Shenzhen (CN)
Publication Details
- Published
- 2024-11-18
- DOI
- https://doi.org/10.1109/a-sscc60305.2024.10849005
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Shenzhen Fundamental Research Program