MOSAIC^®: Chiplet Architecture Based on Die-to-Die Interface for CXL^®Memory Applications and Limitations in Bandwidth, Latency, and Power

This paper proposed a chiplet architecture for large capacity CXL® (Compute Express Link) [1] memory applications based on MOSAIC® (Modular Object-oriented Scalable Architecture for Incremental Change) and M.Link (MOSAIC Link) which are SK hynix Inc.'s chiplet architecture and D2D (Die-to-Die) interface based on <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{UCIe}^{\mathrm{T}\mathrm{M}}$</tex> (Universal Chiplet Interconnect Express) [2] and explained limitations in performance, power, and area caused by interconnections and functions between dies. The chiplet package which consists of two same chips, a primary and a secondary, communicates with hosts and media with more channels and bandwidth to support large capacity memories. M.Link, which is composed of Link and PHY layers of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{UCIe}^{\mathrm{T}\mathrm{M}}$</tex> and application layers, interconnects two chips with 0.8pJ/bit of energy efficiency and 17n<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$s$</tex> of latency. CMM® (CXL® Memory module) composed of a chiplet package of the controller and up to twenty DRAM (Dynamic Random Access Memory) packages on E3.S module achieved 12.5GB/s per channel using 32GT/s of PCIe Gen5, 4800MT/s of DDR, and 8GT/s of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{UCIe}^{\mathrm{T}\mathrm{M}}$</tex>. The low power mode using latched receivers and FOWLP (Fan-Out Wafer Level Package) can reduce more power dissipation up to 20% with no degradation in signal integrity.