Comparative Analysis and Implementation of Energy-Quality Scalable Multiply-Accumulate Architectures for TinyML Applications

Recent trends in machine learning algorithms have shifted from computer vision applications to near-sensor intelligent data analytics, such as wireless sensor nodes, which are considered as ultra-low power devices. This shift presents new challenges in energy consumption, throughput, and area budgets. This work implements and optimizes Bit Fusion, a 2D-scalable divide-and-conquer (D&C) MAC architecture with precisionscaling from 8 to 2 bits, through bitwidth optimizations and by trading-off complexity overheads that are not aligned with the target MobileNet-v2 model. The designs are synthesized using 22-nm FD-SOI CMOS technology. It was determined that the throughput trade-offs of 1-level architectures in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{2 b} \times 2 \ \text{b}$</tex> mode for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1 7. 3 7 \%}$</tex> less energy per operation and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{2 6. 8 4 \%}$</tex> more throughput per area would be preferred. Architecture variations were also explored wherein sum-together (ST) architectures outperformed sum-apart (SA) architectures with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{2 1. 0 3 \%}$</tex> reduction in energy per operation and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{3 3. 3 2 \%}$</tex> increase in throughput per area.