A 0.6V Fully-Integrated BLE Transmitter in 65nm CMOS Using a Common-Mode-Ripple-Cancelled Hybrid PLL and a Duty-Cycle-Controlled Class-E/F₂ PA Achieving 25% System Efficiency at 0dBm

Low-cost high-efficiency BLE transmitters (TXs) are highly demanded for short-range wireless connectivity. The system efficiency of previous BLE TXs is mainly limited by PLL and PA performance to satisfy BLE requirements [1]–[3]. In this work, a 0.6 V fully-integrated BLE TX shown in Fig. 1 is proposed to achieve 25% system efficiency at 0 dBm output with following features: (1) a submW RDAC-based hybrid PLL [4] with common-mode (CM) ripple cancellation to reduce reference spur; (2) a switching current-source (SCS) D/VCO with a step-up transformer and a shared bias resistor for differential varactors to improve efficiency and phase noise; (3) a duty-cycle controlled class-E/F<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> digital PA to suppress $3^{\text {rd }}$-harmonic distortion $\left(\mathrm{HD}_{3}\right)$ without degrading PA efficiency; (4) a calibration-free 1-bit $\Delta \Sigma$ high-pass modulation with FIR filtering to overcome the nonlinearity issue of a low-voltage DCO in two-point modulation [5].