Iterative Frequency Tuning Targeting Energy Efficiency Ratio for FPGA-Based Post-Quantum Cryptographic Cores

Electronic Design Automation tools such as high-level synthesis (HLS) have raised the level of abstraction, allowing the use of FPGAs in multiple domains, including post-quantum cryptography (PQC). Among power performance area (PPA) tradeoffs, the energy efficiency ratio is of increasing interest, especially with the need to integrate PQC cores into battery-powered portable appliances. Nevertheless, to target energy efficiency at the HLS level, post-place, and route metrics should be taken into account, which is extremely time-consuming. In this paper, we developed an iterative frequency tuning framework capable of extracting the best quality, energy-efficient design in logarithmic time complexity, converging to the best design frequency with a speedup of 2.89× with respect to the classical approach. The framework also allows the selection of the criticality of each metric thus altering the design cost function to suit the requirements of the HLS designers. The framework and the results will be released as open-source, allowing HLS designers to design the highest energy efficiency ratio PQC cores quickly.