A reduced complexity MLSD-based adaptive Duo-PAM4 detector in 28-nm CMOS for 56-Gb/s wireline receiver

The bandwidth demand for long-reach (LR) PAM4 wireline transceivers is growing rapidly. When the channel insertion loss (IL) is greater than 20 dB, the increased inter-symbol interference (ISI) associated with a high bit rate can greatly increase the bit error rate (BER) [1]. The duobinary four-level pulse amplitude modulation (Duo-PAM4) signal has a lower bandwidth compared to the PAM4 signal and is studied in high IL and high-speed serial links [2–4]. However, its more complex structure makes it more demanding in terms of equalization capability. The conventional decision feedback equalization (DFE) approach is difficult to implement in high-speed wireline transceivers due to its short feedback loop and propagation of errors [5]. In this paper, we propose a reduced branch maximum likelihood sequence detector (RB-MLSD) for Duo-PAM4 for high-speed ADC-DSP transceivers, which accomplishes both detection and decoding simultaneously and avoids the disadvantages of timing constraints and error propagation of the conventional DFE and slicer scheme. Meanwhile, we propose an improved zero-forced algorithm for Duo-PAM4 (ZF-Duo-PAM4), which reduces the problem of long convergence time of the FFE tap coefficient when the conventional ZF algorithm is applied to Duo-PAM4.