A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier with Ground Precharge and Charge Transfer Pre sensing for Sub-1V DRAM

Over the past two decades the DRAM products have consistently decreased the supply voltage for advances in the energy required to access and store data in memory cells. In addition, as the DRAM technology scales, the capacitance (Cs) to store data polarity gradually decreases and the discrepancy of the transistor’s key parameters, such as threshold voltage, increases. Therefore, bit-line sense amplifier (BLSA) with high sensitivity is essential. Traditionally, the BLSAs rely on cross-coupled latch with $\mathrm{V}_{\mathrm{cca}} / 2$ precharge topology due to their balanced characteristic between data “ 1 “ and “ 0 “, and many studies have been investigated to improve its sensitivity. Fig. 1(a) shows the prior offset compensation sense amplifier (OCSA). To mitigate the BLSA’s offset, $\phi_{1}$ is tuned on before the enabling word line (WL) and at the end of $\phi_{1}$ phase the offset of BLSAs is minimized [1], [4]. The OCSA offers a sensitivity solution and benefit from fast settling speed using positive feedback during the offset compensation phase. However, with the low supply applications, high-speed operation and device reliability are limited due to the $\mathrm{V}_{\mathrm{cca}} / 2$ precharge topology.