A 0.91-pJ/b 20.8–32-Gb/s Reference-Less Sub-Baud-Rate CDR Circuit

Clock and data recovery (CDR) circuits are widely used in multi-standard transceivers. To improve the energy efficiency of 2 x oversampling phase detectors (PDs) in digital CDR circuits, a baud-rate PD [1], and sub-baud-rate PDs [2]–[4] are presented to reduce the required number of sampling clock phases and clock buffers. Some CDR circuits use frequency detectors (FDs) [1], [3] to extend the frequency capture range (FCR) in multi-standard applications. However, additional slicers or hardware are required, which degrade the energy efficiency. In this work, a sub-baud-rate reference-less CDR circuit using six slicers and an active differentiator is presented to improve energy efficiency. Since the number of slicers is reduced, the output capacitive load of the continuous-time linear equalizer (CTLE) is improved. To extend the CTLE’s bandwidth, an active inductor and a negative capacitor are used. A sub-baud-rate FD is also realized by sharing the slicers of the sub-baud-rate PD.