A Fully Integrated 433.92 MHz PPM Transmitter with 16.9 dBm Output Power and 210 nJ/Bit Efficiency
This paper presents a low-power 433.92MHz Pulse Position Modulation (PPM) transmitter designed using the TSMC 65nm CMOS technology. The transmitter primarily comprises a Phase-Locked Loop (PLL) frequency synthesizer, a Pierce Oscillator responsible for generating the PLL reference clock, and a Class-E power amplifier (PA). Notably, all components of the implemented transmitter ASIC feature enable/disable functionality to facilitate Pulse Position Modulation (PPM) implementation. While the transmitter is fully integrated on a chip, excluding the PI load impedance matching network and load capacitors of the Pierce Oscillator, post-simulation results indicate a PLL locked time of approximately 5μs. The transmitter exhibits a power consumption of 140.94mA at a 1.2-volt supply, with the PA delivering an output power of +16.9dBm. The overall footprint of the transmitter is compact, measuring 0.8mm × 1mm, inclusive of ESD pads.
Authors
- A. Basçhirotto (ORCID: https://orcid.org/0000-0002-8844-5754)
- Syed Usman Amin (ORCID: https://orcid.org/0000-0001-5770-3100)
Institutions
- University of Milano-Bicocca (IT)
Publication Details
- Published
- 2024-11-18
- DOI
- https://doi.org/10.1109/icecs61496.2024.10849200
- Citations
- 1
- Primary Topic
- Radio Frequency Integrated Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.21