A 200Gb/s, 3.5pJ/bit Monolithically Integrated WDM SiPhotonic Transceiver for Chiplet Optical I/O

Silicon photonics (SiPh) technology fabricates both electronic and photonic circuits on the same CMOS wafer, enabling the optical transceivers integrate into the xPU’s package as embedded I/O [1]. By directly attaching fiber to the chip edge, the interconnect reach is extended and the energy efficiency is significantly improved. Previous works have demonstrated the hybrid integration of separate electronic and photonic chips in different processes [2] [3] [4]. As illustrated in Fig. 1, hybrid integration inevitably introduces significant parasitic capacitance due to the presence of ESD and I/O pads, which degrade signal integrity and energy efficiency. Previous monolithic integration of micro-ring (MR) WDM transceivers has demonstrated that these issues can be effectively overcome, but their speed is limited to a maximum of 32Gbps/channel [5]. As transmission speeds increase, several issues arise, as illustrated in Fig. 1: (1) To ensure the signal-to-noise ratio (SNR) of the modulated signal and meet the input sensitivity requirements of the receiver (RX), the transmitter (TX) needs a higher extinction ratio (ER). This often requires the microring modulator (MRM) to be biased at a higher insertion loss(IL), leading to a non-linear and limited electro-optic(EO) response. (2) To reduce inter-channel crosstalk, the RX employs a sharp roll-off micro-ring resonator (MRR) to prevent spectral leakage from adjacent wavelengths. But narrow full width at half maximum (FWHM) can result in signals with insufficient bandwidth after demultiplexing.