A 900-MHz Hardening-by-Design Voltage Controlled Oscillator in 28nm CMOS

In this paper we present the design and electrical simulations of a Hardening-by-Design current starved Voltage Controlled Oscillator (VCO). This VCO is designed to be a core component of a rad-hard Phase Locked Loop (PLL) functioning as a clock generator with a target output frequency of 900 MHz. The VCO is realized as a 4-stage fully differential ring oscillator in 28 nm CMOS <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{HPC+}$</tex>. Its performances have been evaluated by extensive simulations in Cadence environment in terms of power consumption <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$({322.6}\ \mu \mathrm{W})$</tex>, phase noise (-83.78 dBc/Hz @ 1 MHz) and jitter (349.1 fsRMS). The impact of a 1 GRAD Total Ionizing Dose (TID) on the threshold voltage of NMOS and PMOS transistors was replicated by working on transistor models. An electrical simulation was performed, along with a comparison between PVT simulations and this supplementary corner analysis. The results show the robustness of the VCO in response to threshold voltage shifts induced by 1 GRAD TID.