A 10 Gb/s Full-Rate Receiver with RX-FFE Compensation

The paper presents a feed-forward equalizer (FFE) at the receiver. The inter-symbol-interference (ISI) can be eliminated by using the analog delay circuit to delay the input signal, and multiply a weight coefficient. Compared with the traditional architecture, it does not need to use the clock for sampling and buffer circuits, so the power consumption can be reduced while maintaining the data amplitude. In addition, the continuous time linear equalizer (CTLE), feed-forward feedback equalizer (FFE) and 1-tap discrete-time decision feedback equalizer (1-tap DT-DFE) are used in data compensation. As a result, the proposed adaptive receiver system not only reduces the complexity of hardware and power consumption but also can be widely used for 7–33 dB channel loss applications. The proposed receiver is fabricated by TSMC 40 nm (TN40G) 1P10M CMOS process. In simulation result, the input is 10 Gb/s PRBS7 NRZ data, and a 10 GHz full rate clock be adopted. In 7-dB channel loss, 22 % improvement in eye height after compensation. In 33-dB channel loss, 47 % improvement in eye height after compensation. The overall power consumption of whole receiver consumes 18.88 mW at 0.9 V supply voltage. The chip area with 40 nm scaling down by 45 nm is 1.060 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and core area is 0.026 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.