A 50kHz-BW 95.4dB-SNDR CT-DT Pipelined Noise-Shaping SAR ADC with Noise-Optimized Two-Stage Dynamic Amplifier

This article presents a highly energy-efficient CT-DT pipelined noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a closed-loop noise-optimized two-stage dynamic amplifier working as the residue amplifier (RA). The sampling-free capacitively-coupled 1st stage breaks the kT/C limit between the SNR and the input capacitor size, thus easing the buffer requirements to drive a large CDAC. Furthermore, a noise-optimized two-stage floating inverter amplifier (FIA) is proposed. It achieves a DC gain of 80.5dB by adopting correlated-level-shifting (CLS) to mitigate the closed-loop gain error. The noise optimization is accomplished by introducing another phase with an extra supply capacitor at the 1st stage, reducing the RA's output noise power by half. Simulated under a 55nm CMOS process, the prototype ADC achieves an SNDR of 95.4dB over a BW of 50kHz while consuming only 79.3µW, resulting in a Schreier figure-of-merit (FoMs) of 183.4dB.