A 22T Static Contention-free Conjoined Master-Slave Flip-flop for Low-Voltage, Low-Power, and Low-Area Applications

Low-voltage flip-flops that operate reliably in a low-voltage regime are crucial for extending battery life in energy-constrained IoT applications. Minimizing dynamic power consumption is also vital for reducing overall SoC power. Additionally, it is important to reduce the area occupied by flip-flops as a significant portion of processor area is dedicated to sequential elements. Prior-art flip-flop designs [1–6] have aimed to be static contention-free (for robustness) and eliminate redundant clock transitions (for low power) simultaneously. However, many failed to meet one of these goals [1–4] or achieved both at a high area cost. This paper introduces a novel design that meets both requirements and achieves a smaller area compared to a conventional Transmission Gate Flip-Flop (TGFF) design.