A 10kHz-BW 24.9μW 90.1dB SNDR Noise-Shaping SAR ADC With Complementary Parametric Amplifiers

Noise shaping successive-approximation-register (NS SAR) analog-to-digital converters (ADC) have shown excellent power efficiency and received popularity in power-constrained designs with high precision requirements, such as loT sensor instrumentation and brain machine interface. Active or passive quantization error amplification is usually required to realize filter shaping [1–2]. The noise and power consumption of the residual amplifier (RA) become one of the important factors limiting the overall ADC performance. Many quantization error amplifiers already exist for design trade-off between power, area and noise, such as duty cycle amplifiers (DCA) [2], gmR amplifiers [3–4], dynamic amplifiers, floating inverter amplifiers (FIA) [5], capacitors stacking [6], etc. In this work, we propose to use passive differential complementary parametric amplifier with kT/C noise dominance and near-zero power consumption to form RA. To demonstrate this technique, an 8 -bit ADC is designed. Fabricated in a typical 180 nm CMOS process, the prototype ADC achieves 90.1 dB SNDR over a 10 kHz bandwidth with an OSR of 12.5 and consumes $24.9 \mu \mathrm{~W}$ from a 1.8 V supply voltage, resulting in a SNDR based Schreier FoM of 176.2dB.