A 1.3mW 10MHz-BW 71dB-SNDR Two-Step TDC-Assisted Continuous-Time Noise-Shaping SAR ADC

NS-SAR ADCs have been a popular choice in various applications due to their excellent power efficiency. Many NS-SAR ADCs have been based on discrete-time (DT) operations (Fig. 1(top)), leading to two critical issues: 1) The kT/C noise from the sampling operation sets the fundamental SNR limit of the ADC. Hence, to achieve a higher SNR, the input sampling capacitor must be increased, posing more power burdens to the input and reference buffers. 2) A strong anti-aliasing filter is required because their STF is unity across all frequency bands. To address these challenges, the design recently reported in [1] demonstrates the feasibility of applying CT operation to the NS-SAR ADC (Fig. 1(middle)). Nevertheless, several challenges still remain: 1) The stride of the ADC’s input DAC decreases at a binary pace as the conversion continues, thus inducing input-dependent errors (EIN). As the number of CT SAR quantizer bits is increased to gain more resolution, $\mathrm{E}_{\mathrm{IN}}$ also increases accordingly, limiting the resolution [2]. 2) The input to the integrator, the residue signal, cannot be available due to its drastic changes during SAR conversion ($\boldsymbol{\phi}_{\text {SAR}}$). This leads to the adoption of a duty-cycled integrator that directs the loop filter input to a virtual ground, thus losing the integration information during $\phi_{\text {SAR}}$. As a result, the system becomes unstable, and the signal transfer function (STF) and noise transfer function (NTF) are degraded if the condition that the proportion of TSAR within T<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</inf> becomes significantly small (less than 5%) can not be guaranteed. Therefore, this limitation makes the design of high-speed CT NS- SAR ADC so challenging.