A Precise and Scalable Biasing Network for Massive Parallel Analog Applications

The demand for computing performance combined with higher energy efficiency is ever-increasing. Analog Computing paradigms are rising in popularity lately because they are potentially faster than digital implementations at a fraction of their energy consumption. For example, so-called oscillator-based Ising machines can solve combinatorial optimization problems very quickly and energy efficiently. They exploit the interaction between hundreds of identical oscillator nodes, forming a large network occupying the usable chip area. Also, spiking neural networks are a promising analog computing approach, which enables machine learning to be performed with low power consumption. Machine learning is currently one of the most significant factors in global energy demand for digital computers. Crucial for the analog computing principle are precise biasing currents because they accurately set mathematical coefficients and references that influence timing behaviors. So, bias current needs to be distributed to the hundreds of nodes spread across the whole die. We analyze two approaches for precise generation and distribution of biasing currents and two calibration methods for comparing and adjusting currents on a local scale and chip scale in the form of a case study on an oscillator-based Ising machine implemented in 28nm CMOS technology and targeting a maximum error of 1.5% while keeping the used area low.