DPe-CIM: A 4T1C Dual-Port eDRAM Compute-in-Memory for Simultaneous Computing and Refresh with Adaptive Refresh and Data Conversion Reduction Scheme

Recently, eDRAM-based computing-in-memory operating in analog domain (ACIM) has been proposed to enhance area and energy efficiency of AI computations [1–5]. However, conventional ACIMs have three challenges. First, previous structures [1–3] have primarily focused on computing area or energy efficiency without considering refresh overhead. This may not be a problem in small DNN models. However, as shown in Fig. 1, refresh overhead has become critical with the increase in DNN model size for higher accuracy and the decrease in data retention time (DRT) due to technology scaling. Second, a pre-measured refresh period at the worst corner used in [4, 5] causes unnecessary energy consumption in most PVT corners, as DRT in eDRAM significantly varies depending on the PVT corner. The last challenge is the significant area and energy overhead of data conversion circuits (DAC or ADC) required in ACIMs to ensure DNN accuracy [4–8].