An 8-bit 20.2fJ/conv-step FoM CI-C Asynchronous SAR ADC with Common-mode Level Shifting

With the recent widespread adoption of DSP-based Serdes and process-in-memory (PIM) technologies, the demand for energy-efficient ADCs with small area and moderate resolution ($5-8$ bits) has increased significantly. For high energy efficiency of ADCs, CDAC-based SAR ADCs have been commonly used, but they are limited in reducing the core area. To improve this, a charge-injection (CI) cell based SAR (CI SAR) ADC [1] was proposed demonstrating high speed of $1 \mathrm{GS} / \mathrm{s}$ and a small core area, but it not only increases the input load due to the large input capacitance, but also has poor linearity due to the common-mode voltage $\mathrm{V}_{\text {cm }}$ variation accompanying the conversion progress, which limits the input signal range narrowly. A 6-bit CI SAR ADC [2] has been proposed to achieve high linearity with a small sampling capacitor while enhancing PVT robustness. This structure applies bias voltage compensation using a replica ADC, and it can shift $\mathrm{V}_{\mathrm{CM}}$ during the conversion. However, different capacitor metals on the p-side and n side are used for small capacitor area, which can affect the linearity at higher resolutions than 6-bit.