A Single-Channel 3.1GS/s 45dB SNDR Pipelined ADC using Amplify-and-Select Structure in 28nm CMOS

A high-speed single-channel ADC is a key building block in highly-parallel TIADCs with sampling rates far beyond tens of GS/s. A faster single-channel reduces the number of channels for the same aggregate sample rate, simplifying design and lowering costs. Traditionally, flash ADCs [1] are the fastest structure but suffer from severe area and power penalties even for medium resolution. Time domain ADCs [2] recently demonstrated multi-GS/s conversion rates, but have yet to surpass limited linearity and PVT sensitivity. Pipelined ADCs are commonly used for balanced performance between speed and linearity, but the conventional design based upon the sequential processes limits itself from reaching higher speed. Prior work [3] tried to break this speed bottleneck by allowing a parallel run of operations using a post-amplification residue generation scheme. This work presents an amplify-and-select stage structure to overcome the speed limitation of the conventional pipelined ADC along with a replica-biased supply-regulation scheme that keeps the common-mode and gain characteristics of dynamic amplifier consistent, which is necessary for the ADC linearity calibration. The prototype ADC at $3.1 \mathrm{GS} / \mathrm{s}$ achieves an effective resolution of 7.28 b over a range of temperatures with state-of-the-art FoMs of 153.7 dB.