SR-Latch-Based 12T SRAM Cell Design for Low Power Application

This paper presents a 12T SRAM cell based on SRlatch design concept, which not only eliminates read disturbances and half-select disturbances, but also achieves stable operation in the sub-threshold region. The design uses additional stacked transistors prevent internal data from read disturbances, thereby increasing the RSNM (Read Static Noise Margin) and enhancing read stability. In addition, the proposed design can reduce the power consumption of bit line switching, enabling operation at low voltages. Based on TSMC 40nm process, the layout of 1-Kb SRAM chip has been implemented and simulation. Its operation voltage is 350mV. When working frequency at 20MHz, the average power consumption is 9.86µW, energy consumption is 0.493pJ, and leakage power consumption is 1.904 µW.