A Compact Low-power 16b SAR ADC using Reservoir-Charge-Redistributed DAC and Configurable Floating-Inverter-Based Comparator
Systems-on-chip applications have become imperative for high-precision ADCs with low power consumption and compact silicon area. SAR ADCs exhibit outstanding energy efficiency but necessitate high fidelity and fast settling reference voltages, often consuming considerable power and/or area. To alleviate such overheads, the passive-charge-sharing SAR ADCs have been reported [1] [2] [3], as shown in Fig.1. However, [1] suffers from a large reservoir capacitor (CREF) to capacitive DAC (CDAC) ratio of 80 for 14-bit resolution, and will further expand to 320 for 16 -bit. It also undergoes input-dependent bit weight errors and SNR degradation due to the shared bit capacitor (cap) and reference cap. While [2] [3] mitigates such constitutes by separating the bit and reference caps, its C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">REF</inf>/C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DACC</inf> still limits to $\geq 8$, owing to the shrunken step size. This work proposes a reservoir-charge-redistributed SAR ADC that preserves the high SNR and linearity natures in [2] and decouples the compromise between the quantization step size and the value of $C_{\text {Ref }}$ in [2] [3], thus significantly suppressing the $C_{\text {ref/ }}$ dad $^{\prime}$ to 0.35 X A configurable floating inverter amplifier (FIA) -based comparator is also presented to improve the energy efficiency further and enable a regular 1.2 V supply implementation, which is different from 3.3 V in [1] [2] [3]. The ADC achieves an 80.9dB SNDR and 100.3dB SFDR at Nyquist input and consumes $291.7 \mu \mathrm{~W}$ power from a single supply at $1 \mathrm{MS} / \mathrm{s}$, yielding a $32.1 \mathrm{fJ} /$ conv.-step FoM<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">walden</inf> and 173.3 dB FoM<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sch</inf>.
Authors
- Zihao Zheng
- Xianghui Pan
- Yan Song (ORCID: https://orcid.org/0000-0001-8380-5944)
- Chi‐Hang Chan (ORCID: https://orcid.org/0000-0002-7635-1101)
- Chenxi Yuan (ORCID: https://orcid.org/0000-0002-4927-709X)
- Yan Zhu (ORCID: https://orcid.org/0000-0002-9610-0641)
- Rui P. Martins (ORCID: https://orcid.org/0000-0003-2821-648X)
Institutions
- University of Macau (MO)
Publication Details
- Published
- 2024-11-18
- DOI
- https://doi.org/10.1109/a-sscc60305.2024.10848951
- Citations
- 2
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.37
Funders
- National Natural Science Foundation of China