A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module

The big-data platforms such as data centers and servers require high-speed, high-density, and low-energy dual in-line memory module (DIMM) including an array of DRAMs mounted on a small board in Fig. 1. Each DRAM is working based on the double data rate (DDR) memory interface to accomplish $2 x$ speed compared to its counterpart, single data rate (SDR). However, the rapidly growing CPU speed has needed more the number of DRAMs on the DIMM board, leading to a necessity of a registering clock driver (RCD) IC [1]. It plays a critical role in connecting the CPU and 40EA DRAMs through a time-interleaved DRAM operation by segmenting the the DIMM board to 2-channels (A, B) and 2-groups (A, B). In other words, the RCD IC should enhance the timing synchronization among memory modules by refining the command-address ($\mathrm{D}_{\mathrm{CA}}$) data and the chip-selection ($\mathrm{D}_{\mathrm{cs}}$) data along with the differential clock ($\mathrm{D}_{\mathrm{ck}}$) from the CPU. Additionally, it significantly contributes to the system stability improvement by ensuring the consistent signal transmissions, but the bandwidth evolution to $4^{\text {th }}$-generation ($7.2 \mathrm{GT} / \mathrm{s}$) causes formidable challenges in processing 7-bit Dca, 2-bit Dcs and 1-differential Dck and transmitting refined 14bit Qca, 2-bit Qcs and 2-differential Qck with the minimal pin-to-pin skew ($\lt \pm 2.5 \mathrm{ps}$) to 40EA DRAMs. To overcome these issues, we present a $7.2 \mathrm{GT} / \mathrm{s}$ RCD IC for the DDR5 DIMM. The proposed timing calibration strategy based on a PVT-insensitive digital-to-time converter (DTC) and a phase-interpolator (PI)-offset control ensures stable data processing of $\mathrm{D}_{\mathrm{CA}}$ and $\mathrm{D}_{\mathrm{cs}}$. The PI-imbedded PLL mitigates the timing slack through jitter-filtering of Dck input (4.72 to $0.20 \mathrm{ps} r \mathrm{~ms}$ at 3.6 GHz). Additionally, the auxiliary-DAC (A-DAC)-based current-mode PI (CMPI) compensates for phase and amplitude distortions of the conventional CMPI, yielding $\mathbb{N L}_{p-p}$ of ${\lt}1.06 \mathrm{LSB}$ at 3.6GHz. Finally, the proposed skew calibration strategy allocating an additional PI-offset control per group and a DTC per pin allows the skew to be $\lt \pm 1.6$ ps.