A 1.2GS/s 11b Time-Interleaved SAR ADC with Low-Cost Derivative-Based Background Timing-Skew Calibration and Variable-Load Comparators

Time-interleaved (TI) SARs are popular choices for high-speed ADCs due to their high energy efficiency and scaling compatibility, but they suffer from timing skew that severely degrades the linearity. The key to the background calibration of the timing skew error $\Delta t$ is to correctly estimate its sign, so that $\Delta t$ can be minimized by adjusting a variable delay line. One way to estimate $\operatorname{sgn}(\Delta t)$ is to add a reference ADC channel (ref-ADC) and compare its output $\mathrm{D}_{\text {ref }}$ with each sub-ADC channel output $D_{i}$ to obtain $\Delta V_{i n}=D_{i}-D_{\text {ref. }}$. However, without knowing the input derivative dV in $/ \mathrm{dt}$, the estimation of $\operatorname{sgn}(\Delta t)$ relies on computing auto-correlation or variance, which takes millions or even billions of samples to converge [1]. Thus, it is preferred to extract both $\Delta \mathrm{V}_{\text {in }}$ and $\mathrm{d} \mathrm{V}_{\text {in }} / \mathrm{dt}$, which allows the direct solving of $\operatorname{sgn}(\Delta t)=\operatorname{sgn}\left(\Delta V_{i n} \cdot d V_{\text {in }} / d t\right)$ and achieves a fast convergence. The derivative can be estimated by using a digital FIR filter, but it is computationally intensive and limits the input bandwidth [2]. It can also be extracted by adding another channel to build an analog derivative filter [3] [4]. This approach supports wide input bandwidth, but two extra channels result in large area and power overhead. To minimize the cost, this paper proposes a novel timing-skew calibration technique that uses only one extra channel to extract both $\Delta \mathrm{V}_{\text {in }}$ and $\mathrm{d} \mathrm{V}_{\text {in }} / \mathrm{dt}$, achieving low-cost and fast calibration. Dummy loads are used to compensate the impedance modulation effect. This paper also proposes a novel variable-load comparator. It outperforms the conventional design in both speed and energy efficiency. Equipped with the proposed calibration technique and comparators, a prototype 1.2GS/s 11b TI SAR ADC with an on-chip timing-skew calibration engine achieves 58.4 dB SNDR while consuming only 4.6 mW, leading to a competitive FoMs of 169.6 dB and FoM w of $5.6 \mathrm{fJ} /$ conv-step.