A 1kHz-to-62MHz 2.06zF_rms Resolution Lock-in Amplifier with SAR-assisted Parasitic and Baseline Capacitance Compensation

The continuous advancement of sensing technology stimulates the demand for high-precision capacitive sensor interfaces for proximity detection, material analysis, and liquid level sensing. The capacitive transimpedance amplifier (C-TIA), based on lock-in sensing principle, can extract sub-fF level capacitance changes in an extremely noisy environment with balanced resolution and speed [1, 2]. However, there are still several design challenges in achieving ultra-high resolution down to zF levels. According to the equivalent capacitance noise equation in Fig.1, the parasitic capacitance $\mathrm{C}_{\mathrm{p}}$ at virtual ground is the first factor that limits the capacitance resolution before calibration. It also reduces the bandwidth and stability of the C-TIA. The second challenge is that the dynamic capacitance of interest $\mathrm{C}_{\mathrm{d}}$ often appears to be several orders of magnitude smaller than the inherent baseline value $\mathrm{C}_{\text {base }}$, calling for a large dynamic range to accommodate both types of capacitances, which imposes stringent requirements on the SNR. Another design challenge pertains to the DC bias of the C-TIA. Conventional pseudo-resistor (PR) for DC biasing is susceptible to significant resistance variation, and can easily saturate the TIA in the case of a nA-level leakage current from the sensor [3]. Although the DC servo loop (DSL) can solve this issue, conventional PR with fixed value still imposes significant constraints on the maximum input DC current. Moreover, the PR’s current noise, positively correlated to the input DC current, can dominant the CTIA’s noise performance [4, 5]. Additionally, addressing the system’s limitations with automatic calibration, rather than manual calibration, is crucial for increasing overall efficiency and user experience.