A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA

Pipelined ADCs have been a preferred architecture for high-resolution and high-speed applications [1], [2]. In typical pipelined ADCs, the residue amplifier (RA) plays a crucial role in determining the overall ADC performance. Closed-loop dynamic RA structures, such as ring amplifiers and floating inverter amplifiers (FIAs), have been actively researched for energy efficiency. Compared with ring amplifiers, FIAs offer inherently stable output common-mode (CM) voltage and attractive power efficiency owing to the self-quenching characteristic. However, pursuing high gain can limit the output swing, as seen in [3] due to the cascode last stage. A Miller-compensated two-stage FIA with a cascode 1st stage achieves wide output swing but is limited to a maximum DC gain of $\sim\left(\mathrm{g}_{m} \mathrm{ro}_{0}\right)^{3}$ [4]. Additionally, FIAs suffer from bandwidth limitations due to the self-quenching. Although ring amplifiers can be alternative choices for high speed [2], they consume static power [1], [2], [5].