A –51dBc-Reference-Spur and 66fs<sub>rms</sub>-Jitter D-Band PLL with Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector

Sub-THz frequencies in the W and D bands have received significant attention, and the scope of their application has been extended to cellular communications, radar, and imaging. For these applications, PLL design is especially important to provide precise clock signals at high frequencies above 100 GHz. Cascaded PLLs using a chain of frequency multipliers (FMs) [1–3] are still popular, but they are inefficient in terms of power and silicon area. Single-stage direct PLLs are better suited, but conventional architectures are limited in achieving low jitter due to their inherently high in-band phase noise (PN) [4]. Using a subsampling PD (SSPD) with a high phase-error ($\phi_{\text {ERR }}$)-detection gain, $K_{\text {PD }}$, SSPLLs can reduce the in-band PN. However, this merit is not valid in the sub-THz band where the value of KPD is reduced significantly by the output pole of the SSPD. To ensure a high $K_{P D}$ at such high frequencies, the power-gating injection-locked FM-based PD (PG-ILFM PD) was presented in [5] (top of Fig. 1). With a strong power-gating injection-locking of the replica VCO (RVCO) by the reference clock ($S_{\text {REF }}$), an ultra-low-jitter, high-frequency reference signal, i.e., Silfm, can be generated, and it can be used to detect the $\phi$ ERR of the output of the main VCO (MVCO), i.e., Sout, much more frequently. Based on this mechanism, the PGILFM PD can secure a high $K_{\text {PD }}$, so the D-band PLL in [5] succeeded in achieving a low RMS jitter. However, the PG-ILFM PD has fundamental problems that are caused by its operation, in which the RVCO oscillates only during a half $T_{\text {REF }}$, causing a binary frequency-shift-keying (BFSK) modulation of the frequency of the MVCO (fout). Due to this problem, the PLL in [5] had a high reference spur, i.e., 42dBc. This half-period operation of the PG-ILFM PD also limited the increase of KPD, preventing the further reduction of the RMS jitter.

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Published
2024-11-18
DOI
https://doi.org/10.1109/a-sscc60305.2024.10849317
Citations
1
Primary Topic
Advancements in PLL and VCO Technologies
Type
article
Field-Weighted Citation Impact
0.21

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article

A –51dBc-Reference-Spur and 66fsrms-Jitter D-Band PLL with Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector

Jaehyouk Choi, Jooeun Bang, Moon‐Ku Han, Seohee Jung et al.
1 citations
Advancements in PLL and VCO Technologies
0.21
article

A –51dBc-Reference-Spur and 66fsrms-Jitter D-Band PLL with Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector

Jaehyouk Choi, Jooeun Bang, Moon‐Ku Han, Seohee Jung, Jae-Ho Kim
article en
1 citations

Abstract

Sub-THz frequencies in the W and D bands have received significant attention, and the scope of their application has been extended to cellular communications, radar, and imaging. For these applications, PLL design is especially important to provide precise clock signals at high frequencies above 100 GHz. Cascaded PLLs using a chain of frequency multipliers (FMs) [1–3] are still popular, but they are inefficient in terms of power and silicon area. Single-stage direct PLLs are better suited, but conventional architectures are limited in achieving low jitter due to their inherently high in-band phase noise (PN) [4]. Using a subsampling PD (SSPD) with a high phase-error ($\phi_{\text {ERR }}$)-detection gain, $K_{\text {PD }}$, SSPLLs can reduce the in-band PN. However, this merit is not valid in the sub-THz band where the value of KPD is reduced significantly by the output pole of the SSPD. To ensure a high $K_{P D}$ at such high frequencies, the power-gating injection-locked FM-based PD (PG-ILFM PD) was presented in [5] (top of Fig. 1). With a strong power-gating injection-locking of the replica VCO (RVCO) by the reference clock ($S_{\text {REF }}$), an ultra-low-jitter, high-frequency reference signal, i.e., Silfm, can be generated, and it can be used to detect the $\phi$ ERR of the output of the main VCO (MVCO), i.e., Sout, much more frequently. Based on this mechanism, the PGILFM PD can secure a high $K_{\text {PD }}$, so the D-band PLL in [5] succeeded in achieving a low RMS jitter. However, the PG-ILFM PD has fundamental problems that are caused by its operation, in which the RVCO oscillates only during a half $T_{\text {REF }}$, causing a binary frequency-shift-keying (BFSK) modulation of the frequency of the MVCO (fout). Due to this problem, the PLL in [5] had a high reference spur, i.e., 42dBc. This half-period operation of the PG-ILFM PD also limited the increase of KPD, preventing the further reduction of the RMS jitter.

Seoul National University (KR), Korea Advanced Institute of Science and Technology (KR)
Seoul National University, National Research Foundation of Korea
Affordable and clean energy
Openalex Percentile: Top 44%
Advancements in PLL and VCO Technologies
0.21
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