A 13.75-14.75-GHz 32.1-fs_RMS Jitter -100.6-dBc Reference Spur -261.4-dB FoM Sub-Sampling PLL Using a KPD-Doubled Isolated Sub-Sampling Phase Detector for Reliable Spur-Jitter-Joint Optimization

With the continuous increase in the communication data rate, low-jitter phase-locked loop (PLL) is increasingly becoming significant for ultra-high-speed wireless or wireline transceivers [1], namely the concurrent realization of low jitter and low spur. The most advanced PLL design has achieved sub-50-fs jitter [2–6], as summarized in Fig.1. The reference sampling PLL (RS-PLL) [2] achieves low jitter and low power due to the removal of input reference clock buffer and its simple architecture. But the clock feedthrough from the reference clock to the tuning voltage of the voltage-controlled oscillator (VCO) limits its spur performance, and the direct sampling operation to the reference clock from crystal induces disturbance to other blocks in the system. The sampling PLL (S-PLL) [3, 4] can avoid these issues, and achieves very low clock jitter using a double-edge sampling phase detector (PD); yet, the PLL in [3] requires a complicated and power-hungry retimer to realize a low-jitter high-frequency divider chain, and the mismatch of duty cycle correction (DCC) circuit degrades the spur to >-70 dBc. Multi-reference PLL (MR-PLL) [5] achieves the state-of-the-art low jitter but it consumes huge power due to the adoption of multiple reference clock sources with multiple SPDs; meanwhile, large numbers of switches in its multiple SPDs also cause higher-level feedthrough to VCO, thus limiting spur. Alternatively, the sub-sampling PLL (SS-PLL) with isolation subsampling PD (iSSPD) achieves sub-35-fs jitter and $\lt-90-\mathrm{dBc}$ spur concurrently with a low-power retime-less divider [6]. However, its spur-jitter-joint optimization relies on an ultra-high VCO swing and small-sized iSSPD to suppress the PD’s interference to VCO with a sufficient iSSPD gain (KPD), hence leading to a reliability issue with a relatively high VCO power.