A 6.1fJ/conv-step 0.0017mm<sup>2</sup> Level Crossing ADC for Compressive Neural Sensing with Event-Driven Ramp Generation and Sparse DAC Switching Scheme
This paper presents a dynamic level crossing ADC achieving a Walden FoM of $6.1 \mathrm{fJ} /$ conv-step and a data reduction of $\gt10 \times$ compared to conventional synchronous ADCs, while occupying an active area of only $0.0017 \mathrm{~mm}^{2}$. Asynchronous event generation within a low frequency clock period is exploited to significantly improve the energy efficiency without compromising in data reduction. To further improve energy efficiency, a novel DAC switching scheme optimized for sparse signals is presented. The presented LC-ADC supports 16 time-multiplexed neural sensing signals.
Authors
- Martijn Timmermans (ORCID: https://orcid.org/0009-0005-4286-7475)
- Pieter Harpe (ORCID: https://orcid.org/0000-0002-6542-0001)
- Yao‐Hong Liu (ORCID: https://orcid.org/0000-0002-3256-6741)
- Eugenio Cantatore (ORCID: https://orcid.org/0000-0002-9646-7232)
- Stan van der Ven (ORCID: https://orcid.org/0000-0002-3387-8384)
- Yuming He (ORCID: https://orcid.org/0000-0002-7812-1916)
- Roland van Wegberg
- Hua-Peng Liaw (ORCID: https://orcid.org/0009-0003-4721-3556)
Institutions
- Imec the Netherlands (NL)
- Eindhoven University of Technology (NL)
Publication Details
- Published
- 2024-11-18
- DOI
- https://doi.org/10.1109/a-sscc60305.2024.10848955
- Citations
- 1
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.18
Funders
- European Commission
- European Research Council