A Compact Neuron Implementation for a Capacitive Analog Neural Network for In-Sensor Processing

Artificial Neural Networks (ANN) are being increasingly applied to process signals from arrays of sensors. Despite the flourishing of hardware accelerators for digital ANN, when the number of inputs increases, the power dissipation in the analog-to-digital conversions of all the signals becomes a bottleneck to power efficiency. Thus, we propose an analog approach to integrate ANN pre-processing directly in the same front-end ASIC used to amplify and filter the signals from large (e.g. 64) arrays of sensors, as in the case of imaging radiation detectors. Here we present a detailed analysis of the limits of a past preliminary charge-mode implementation of an ANN (with 130 neurons) and present a novel, improved topology of the neuron. The charge integrator is here realized with an inverter in order to achieve an improved non-linear sigmoidal activation function, while weighting is based on a compact C-2C DAC topology. Compared to the previous implementation the area occupation and the power dissipation faced a reduction by 94% and 90% respectively. The estimated efficiency of the proposed network is 3.5 TOPs/W.