Realization of Memristor Ratioed Logic with HfO₂-Based Resistive RAM

Emerging nonvolatile memristive memory technologies, such as resistive RAM, offer the potential to perform logic gate operations. One prominent technique is Memristor Ratioed Logic (MRL), which belongs to the non-stateful CMOS counterpart logic group. MRL can execute AND and OR functions using two memristors as voltage dividers. Since both input and output instances are represented as voltages, MRL gates can be seamlessly integrated with CMOS logic, allowing for the construction of complete logic circuits using CMOS inverters. This paper experimentally demonstrates MRL gates based on Hf0<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> memristors within a crossbar array. We validate the functionality of these gates and identify their limitations, including the nonlinearity, the lack of signal restoration, and certain reliability issues. Additionally, we introduce a memristor initialization mechanism that simplifies the switching process, enhancing the overall performance and reliability of MRL gates.