A Quasi-Delay-Insensitive 3D Interconnect for Robustness Against Delay Uncertainties Using a 7nm Face-to-Face Wafer Bonded Process

We present a quasi-delay-insensitive (QDI) circuit designed to provide a correct-by-construction cross-die link in a 3D augmented reality system-on-chip (SoC) in a 7nm hybrid-bonding face-to-face wafer bonded process. The circuit can operate at sub-threshold voltages, down to 0.235V, with a minimum energy point of 0.141pJ/B at 0.45V. Silicon measurements in 7nm technology demonstrate the circuit's ability to cope with delay variations, which are exacerbated in sub-threshold voltages, and to reach minimum energy voltage, which is not possible in equivalent synchronous links of the SoC.