A 5× OSR 1MHz-BW 81dB-SNDR 5^th-Order Noise-Shaping SAR ADC with Zero-Optimized 3^rd-Order Integrator

Noise-shaping (NS) SAR ADCs have become very popular architecture for their low-power high-resolution characteristics. However, designing a highly energy-efficient NS SAR with low OSRs is challenging. It requires simple and low-power hardware to achieve high-order optimized noise transfer functions (NTF) that maximally preserves the efficient nature of the SAR. Classic single-loop NS designs typically employ CIFF structure, but the complexity of the NS filter increases drastically with the NTF order [1]. A recent work in [2] reported a $4^{\text {th }}$-order NS having an aggressive NTF utilizing a buffer-assisted CIFF structure with only simple open-loop amps. However, it lacks NTF optimization capability, making it unsuitable for low-OSR designs. In addition, the static power consumption by the buffers degrades the energy efficiency. Another work in [3] presented a low-complexity cascaded EF structure where a $4^{\text {th }}$-order NTF was implemented by nesting two simple $2^{\text {nd }}-$ order filters with comparable hardware overhead to that of $2^{\text {nd }}$-order NTF. Nevertheless, this structure suffers from SQNR fluctuation and relatively low offset tolerance.