A Memristor Variation-Aware Analog Memristor Programming Circuit for Associative Memories

In the emerging realm such as in-memory computing and associative memories, the application of memristors necessitates the development of high-performance programming circuits for effective weight updates. The conventional Program-Verify (PV) method requires complex memory peripherals and data converters, which is a major bottleneck for area and power efficiency. Moreover, memristor variability critically undermines the efficacy of AI applications utilizing memristive technology. Addressing these challenges, this paper introduces a novel analog memristor programming circuit that takes memristor variations into account. Leveraging the TSMC 28nm process PDK and the JART VCM vlb var memristor model for simulations, our circuit achieves ±1 µS error margin for over 98.5% of programming results without using ADCs. When contrasted with preceding studies, the proposed solution not only reduces the programming settling time by 15.0% to 87.5% but also exhibits comparable performance to the PV method designed with the same semiconductor and memristor technology.