22-nm Data Backup SRAM Using 3.3V IO MOSs with Ultralow-Voltage-Drop Erasure Technique for Secure IoT Applications

A new erasure technique in terms of ultralow voltage drop is proposed for data backup SRAM (DBRAM). After a tampering event is detected, the proposed macro erases all of the data stored in cells for a short period equivalent to 3 cycles with the same peak current as that of the normal SRAM read and write operations. As a result, the DBRAM can achieve erasure function even in a limited power supply condition such as battery-operated loT devices. The power performances and peak current characteristics are computationally analyzed and experimentally verified using the fabricated test chips in 22 nm CMOS process.